The accurate operation of differential comparators implemented using two source coupled pairs depends on good matching of the tail current sources. Such comparators can have poor rejection of the common mode signals, especially at low voltages. The poor rejection at low voltages is due mainly to the difficulty of biasing matched current sources well because of reduced voltage headroom available at low voltages.
Common mode differences can also result for several reasons. For example, if the two differential input signals come from circuits powered by two different power supplies, the finite voltage drop on the ground line can result in common mode differences. In addition, common mode difference can result from mismatches of the devices that generate the common voltage.
For the above reasons, a low voltage differential comparator can have a large offset appearing at its output. As an example, if offset appears at a differential output of a circuit, the difference between differential outputs may be taken to be positive when, had it not been for the offset, the output would have been negative. If the circuit is a comparator, the comparator (at a latch stage) may mistakenly output a high signal (e.g., the first differential output is greater than the second differential output) instead of a low signal.
It is therefore an object of the present invention to provide a differential comparator that is less sensitive to common mode differences.